The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a dynamic memory cell with a bit line sense amplifier which steadily operates even at a low voltage.
This application is based on Japanese Patent Application No. 9-149159, filed Jun. 6, 1997, the content of which is incorporated herein by reference.
Along with the advance in manufacturing techniques relating to a semiconductor device, the scales of elements used in semiconductor memory devices are being decreased. Accordingly, with a conventional power supply voltage Vcc, the field density at each portion of the element is too high, and the reliability of the device is degraded. To suppress the degradation of the reliability, the operation power supply voltage Vcc is decreased. For example, the power supply voltage is 5V in a 1-Mbit DRAM, but 3.3V in most 16-Mbit DRAMs mass-produced at present.
The decrease in power supply voltage Vcc yields a secondary advantage, i.e., reduction in power consumption. Therefore, the technique of decreasing the power supply voltage Vcc is important in the fields of semiconductor memory devices and semiconductor integrated circuit devices.
Recently, portable data processing devices such as a PDA (Personal Digital Assistants) are rapidly spread because of small sizes, high performance, and advanced functions. Particularly in recent years, along with the advance in functions, semiconductor memories such as a DRAM are also incorporated in the internal systems of portable data processing devices.
To realize smaller-size, higher-performance portable data processing devices with more advanced functions, the operation voltage of the semiconductor memory is further decreased. That is, the power supply voltage is decreased from 3.3V to 1 to 1.5V. As a result, the portable data processing device can be further decreased in power consumption and can operate with a battery.
In addition, ultra-low-power-supply-voltage operation semiconductor memories which operate at a power supply voltage Vcc of 1V or less are also developed. Such a semiconductor memory is useful in not only portable data processing devices but also other electronic devices.
As the power supply voltage Vcc decreases to a low or ultra low voltage, it becomes difficult to meet demands for a bit line sense amplifier, i.e., to detect and amplify a small data signal from a memory cell.
A typical bit line sense amplifier will be described below.
FIG. 18 is a circuit diagram of a typical bit line sense amplifier used in a conventional DRAM. FIG. 19 is an operation waveform chart of the sense amplifier.
The circuit arrangement will be explained.
As shown in FIG. 18, a bit line BL connected to a dynamic memory cell MC1 and an inverted bit line /BL ("/" means "inverted" hereinafter) connected to another memory cell MC2 are arranged. The bit line BL and the inverted bit line /BL are paired (to be referred to as a pair of bit lines hereinafter).
The memory cell MC1 comprises a transfer gate transistor TR1 and a memory capacitor C1. The transfer gate transistor TR1 has a current path and a gate electrode connected to a word line WL1. One end of the current path is connected to the bit line BL. Two electrodes of the memory capacitor C1 are connected to the other end of current path of the transfer gate transistor TR1 and a plate electrode, respectively. The electrical charge of memory data is stored at a contact node of the TR1 and C1 (a storage node). The plate electrode receives a plate voltage VPL. Similarly, the memory cell MC2 comprises a transfer gate transistor TR2 and a memory capacitor C2. The transfer gate transistor TR2 has a current path and a gate electrode connected to a word line WL2. One end of the current path is connected to the inverted bit line /BL. Two electrodes of the memory capacitor C2 are connected to the other end of current path of the transfer gate transistor TR1 and a plate electrode, respectively. The electrical charge of memory data is stored at a contact node of the TR2 and C2 (a storage node). The plate electrode receives the plate voltage VPL.
The pair of bit lines are connected to a bit line pair equalizer 10, an n-type sense amplifier 11, and a p-type sense amplifier 12.
The bit line pair equalizer 10 comprises an n-channel MOSFET (to be referred to as an nMOS transistor hereinafter) N3 with a current path series-connected between the bit line BL and the inverted bit line /BL, an nMOS transistor N4 which has one current path end connected to the bit line BL and receives, at the other end, an intermediate voltage Vcc/2 between a high voltage Vcc and a low voltage Vss (for example, ground voltage), and an nMOS transistor N5 which has one current path end connected to the inverted bit line /BL and receives the intermediate voltage at the other end. The gates of the NMOS transistors N3 to N5 receive a precharge signal PRC.
The n-type sense amplifier 11 comprises an nMOS transistor N1 with one current path end connected to the bit line BL and a gate connected to the inverted bit line /BL, and an nMOS transistor N2 with one current path end connected to the inverted bit line /BL and a gate connected to the bit line BL. The other end of the current path of each of the nMOS transistors N1 and N2 is connected to a activating node SAN.
The activating node of the n-type sense amplifier 11 SAN is connected to the intermediate voltage Vcc/2 via a switch SW1N and the low voltage Vss via a switch SW2N.
The p-type sense amplifier 12 comprises a p-channel MOSFET (to be referred to as a PMOS transistor hereinafter) P1 with one current path end connected to the bit line BL and a gate connected to the inverted bit line /BL, and a pMOS transistor P2 with one current path end connected to the inverted bit line /BL and a gate connected to the bit line BL. The other end of the current path of each of the pMOS transistors P1 and P2 is connected to a activating node SAP.
The activating node of the p-type sense amplifier 12 SAP is connected to the intermediate voltage Vcc/2 via a switch SW1P and the high voltage Vcc via a switch SW2P.
The operation will be explained.
As shown in FIG. 19, the word line WL1 is at the low voltage Vss during the standby period (precharge period). The switches SW1N and SW1P are ON, and the switches SW2N and SW2P are OFF. With this setting, the activating nodes SAN and SAP are at the intermediate voltage Vcc/2. The precharge signal PRC is at the high voltage Vcc. The voltages of the pair of bit lines BL and /BL are equalized to the intermediate voltage Vcc/2.
After the precharge period, the read/write period (active period) starts. When the precharge period shifts to the read/write period, the precharge signal PRC first changes to the low voltage Vss. The switches SW1N and SW1P are turned off, and the activating nodes SAN and SAP are disconnected from the intermediate voltage Vcc/2. If the word line WL1 of all word lines is selected, its voltage rises to an active voltage of the word line VWLH higher than the high voltage Vcc. Data corresponding to the storage charge amount is previously written and stored in the storage node electrode SN1 of the memory cell MC1. During a read period, the voltage of the word line WL1 rises to the voltage VWLH to turn on the transfer gate transistor TR1 of the memory cell MC1, and the electrical charge written in the storage node electrode SN1 is transmitted to the bit line BL. As a result, the voltage of the bit line BL slightly changes. When data "1" is written in the storage node electrode SN1, the voltage of the bit line BL rises by +.DELTA.V; when data "0" is written in the storage node electrode SN1, the voltage of the bit line BL falls by -.DELTA.V. FIG. 19 exemplifies the case wherein the voltage rises by +.DELTA.V. The voltage .DELTA.V and a memory capacitor CS/bit line capacitor CB have a relationship of .DELTA.V=(CS/CB).times.(Vcc/2).
After the data of the memory cell is transferred to the bit line, the switches SW2N and SW2P are turned on. Then, the activating node SAN is connected to the low voltage Vss, and the activating node SAP is connected to the high voltage Vcc. The sense amplifiers 11 and 12 are activated. The voltage of the bit line BL further rises from (Vcc/2)+.DELTA.V to the high voltage Vcc, whereas the voltage of the inverted bit line /BL falls from Vcc/2 to the low voltage Vss, thereby amplifying the potential difference between the pair of bit lines. The amplified potential difference between the pair of bit lines is transmitted as readout data to a data line (not shown). In addition, the potential difference between the pair of bit lines is latched by the sense amplifiers 11 and 12 while they are activated. Using the latched voltage Vcc of the bit line BL as data to be restored in the memory cell MC1, data "1" is restored in the memory cell MC1.
The principle of voltage amplification by the sense amplifier will be described with reference to the n-type sense amplifier 11 (nMOS transistors N1 and N2 and activating node SAN) shown in FIG. 18 for the sake of simplicity.
FIGS. 20A and 20B are views for explaining the principle of voltage amplification. FIG. 20A is a view showing a state before the sense amplifier is activated, and FIG. 20B is a view showing a state during activation of the sense amplifier.
As shown in FIG. 20A, before the n-type sense amplifier 11 is activated, the bit line BL is at a voltage of (Vcc/2)+.DELTA.V, the inverted bit line /BL is at the voltage Vcc/2, and the activating node SAN is at the potential Vcc/2.
Thereafter, as shown in FIG. 20B, the voltage of the activating node SAN decreases to Vss, and the n-type sense amplifier 11 is activated. After the voltage of the activating node SAN decreases to Vss, the voltage (corresponding to the amount of charges) of the bit line BL tends to be decreased to the low voltage Vss as BL is discharged toward Vss via the nMOS transistor N1. Similarly, the voltage (corresponding to the amount of charges) of the inverted bit line /BL tends to be decreased to the low voltage Vss as /BL is discharged toward Vss via the nMOS transistor N2. As for the nMOS transistor N2, a source S2 is at the voltage Vss, and a gate G2 is at the voltage of (Vcc/2) +.DELTA.V. As for the nMOS transistor N1, a source S1 is at the voltage Vss, and a gate G1 is at the voltage Vcc/2. In other words, a potential difference VGS between the gate and source of the nMOS transistor N2 is larger than that of the nMOS transistor N1. In this state, the nMOS transistor N2 has a higher current activating ability than that of the nMOS transistor N1. Therefore, the voltage (corresponding to the amount of charges) of the inverted bit line /BL is decreased to the low voltage Vss as /BL is discharged toward Vss via the NMOS transistor N2 prior to the voltage (corresponding to the amount of charges) of the bit line BL. The decrease in voltage of the inverted bit line /BL decreases the voltage of the gate G1 of the NMOS transistor N1. The current activating ability of the nMOS transistor N1 starts lowering. As the current activating ability of the NMOS transistor N1 lowers, the difference in current activating ability between the nMOS transistor N2 and the nMOS transistor N1 is increased more and more. As a result, the voltage of the inverted bit line /BL comes close to the low voltage Vss quickly than that of the bit line BL.
Also in the p-type sense amplifier 12, the voltage of the bit line BL comes close to the high voltage Vcc faster than that of the inverted bit line /BL in accordance with an operation principle symmetrical to that of the n-type sense amplifier 11.
When the voltage of the bit line BL reaches Vcc, and that of the inverted bit line /BL reaches Vss, charging of the bit line BL from the activating node SAP and discharging of the inverted bit line /BL to the activating node SAN stop.
The principle of voltage amplification by the sense amplifier has been described above.
In the typical sense amplifier, if the power supply voltage Vcc decreases to, e.g., 1 to 1.5V, the voltage VGS (=(Vcc/2)-Vss) across the gate and source of each of the nMOS transistors N1 and N2 decreases, resulting in lower current activating abilities of the nMOS transistors N1 and N2 than the conventional case. This delays the voltage amplification operation of the sense amplifier.
If the power supply voltage Vcc further decreases to 1V or less, the nMOS transistors N1 and N2 may not operate satisfactorily because the threshold voltages of the nMOS transistors N1 and N2 become higher than the voltage VGS across the gate and source. In this state, even if the voltage of the activating node SAN is connected to Vss, only a voltage VDS across the source and drain of each of the nMOS transistors N1 and N2 changes to (Vcc/2)+.DELTA.V or Vcc/2, so the inverted bit line /BL cannot be effectively discharged to the activating node SAN. Therefore, the voltage amplification speed of the sense amplifier further decreases.
To solve this problem, the threshold voltages of the nMOS transistors N1 and N2 suffice to be set low. In general, however, they must be 0.4 to 0.5V or more because lower threshold voltages of the nMOS transistors N1 and N2 generate a subthreshold leak current between the high voltage Vcc and the low voltage Vss in the sense amplifier made up of the n-type sense amplifier 11 and the p-type sense amplifier 12, i.e., of the CMOS circuit. Moreover, a similar subthreshold leak current is generated in a peripheral circuit using an nMOS transistor formed in the same manufacturing process as the nMOS transistors N1 and N2. As is well known, the subthreshold leak current increases the power consumption.
A sense amplifier for solving the problem caused by an ultra-low power supply voltage Vcc is reported in M. Nakamura et al. "A 29 ns 64 Mb DRAM with Hierarchical Array Architecture", ISSCC 95. In the sense amplifier reported in this reference, the activating node SAP is temporarily connected to a voltage Vcc2 higher than the memory cell data "1", i.e., the high voltage Vcc to increase the voltage VGS across the gate and source of each of the pMOS transistors P1 and P2 of a p-type sense amplifier at the start of activating the sense amplifier.
The principle of voltage amplification by this sense amplifier will be briefly described in correspondence with the sense amplifier shown in FIGS. 18 and 19.
FIG. 21 is a circuit diagram of a conventional bit line sense amplifier of a DRAM and its peripheral circuit. FIG. 22 is an operation waveform chart of the sense amplifier. The same reference numerals as in FIGS. 18 and 19 denote the same parts in FIGS. 21 and 22, and only a difference will be explained.
As shown in FIG. 21, the circuit is different from that shown in FIG. 18 in that the activating node SAP is connected via a switch SW3P to the voltage Vcc2 higher than the high voltage Vcc.
The operation will be explained below.
As shown in FIG. 22, the word line WL1 is at the low voltage Vss during the precharge period. The switches SW1N and SW1P are ON, and the switches SW2N, SW2P, and SW3P are OFF. With this setting, the activating nodes SAN and SAP are at the intermediate voltage Vcc/2.
After the precharge period, the read/write period (active period) starts. When the precharge period shifts to the read/write period, the precharge signal PRC first changes to the low voltage Vss. The switches SW1N and SW1P are turned off, and the activating nodes SAN and SAP are disconnected from the intermediate voltage Vcc/2. After that, the word line WL1 is selected, and its voltage increases to an active voltage of the word line VWLH higher than the high voltage Vcc. Data written in the storage node electrode SN1 is transferred to the bit line BL, and the voltage of the bit line BL slightly changes within the range of .+-..DELTA.V. FIG. 22 exemplifies the case wherein the voltage rises by +.DELTA.V. Upon the slight change in voltage of the bit line BL, the switch SW3P is turned on to connect the activating node SAP to the sufficiently high voltage Vcc2. At this time, the difference between the voltage Vcc/2 of the inverted bit line /BL and the voltage Vcc2 of the activating node SAP becomes more than the voltage Vcc/2. The potential difference VGS=Vcc2-(Vcc/2) between the gate and source of the PMOS transistor P1 becomes more than the threshold voltage of the PMOS transistor P1, and the p-type sense amplifier 12 starts satisfactorily amplifying the voltage. The p-type sense amplifier 12 starts charging the bit line BL to the sufficiently high voltage Vcc2 via the pMOS transistor P1 prior to the inverted bit line /BL in accordance with the principle of voltage amplification described above. Accordingly, the voltage of the bit line BL rises. By the raised voltage of the bit line BL, the potential difference between the gate and source of the nMOS transistor N2 exceeds the threshold voltage of the nMOS transistor N2. Then, the n-type sense amplifier 11 starts satisfactorily amplifying the voltage. The n-type sense amplifier 11 discharges the inverted bit line /BL to the low voltage Vss via the nMOS transistor N2 prior to the bit line BL in accordance with the principle of voltage amplification described above. After the potential difference between the pair of bit lines is satisfactorily amplified in this manner, the switch SW3P is turned off, and the switch SW2P is turned on, thereby decreasing the voltage Vcc2 of the bit line BL to the high voltage Vcc. Using the latched high voltage Vcc of the bit line BL as data to be restored in the memory cell MC1, data "1" is restored in the memory cell MC1.
In this sense amplifier, at the start of activating the sense amplifier, the activating node SAP is increased to the sufficiently high voltage Vcc2 to drive the p-type sense amplifier 12 first and to raise the voltage of the bit line BL. Using the raised voltage of the bit line BL, the n-type sense amplifier 11 is activated.
By this method, the potential difference between the pair of bit lines can be amplified by the sense amplifier even when the power supply voltage Vcc is decreased to twice or less the threshold voltage of the nMOS transistors N1 and N2.
However, in the bit line sense amplifier with an ultra-low operation voltage which can be used in a semiconductor memory wherein the p-type sense amplifier is first operated, the following technical difficulty is found: the operation margin is smaller than that of a typical sense amplifier not having three power sources for p-type sense amplifier such as shown in FIG. 21.
By the conventional semiconductor manufacturing technique, the threshold voltage in the whole chip or whole wafer varies more in the pMOS transistor whose threshold is difficult to control to be an uniform value than in the nMOS transistor.
In the sense amplifier (FIG. 21) which operates at an ultra-low voltage, the p-type sense amplifier 12 is operated prior to the n-type sense amplifier 11 in order to raise the bit line voltage. In other words, the pMOS transistor whose threshold voltage varies over a wide range performs the initial operation of voltage amplification.
During operation of the sense amplifier, the sense amplifier may erroneously operate if two, paired transistors are different in threshold voltage owing to manufacturing conditions. More specifically, as described above, according to the operation principle of the sense amplifier, the charges of the memory cell are transferred to the bit lines to amplify a small potential difference between the pair of bit lines by the difference between two activating abilities with gate electrodes connected to the bit lines. If the threshold voltage varies to be higher than the slight signal voltage, the signal cannot be accurately amplified, decreasing the operation margin. Therefore, to ensure the operation margin, the signal voltage must be sufficiently set higher than variations in threshold voltage of the transistor caused during the manufacture.
In a conventional sense amplifier which can operate at an ultra-low voltage and performs the initial operation of voltage amplification by a pMOS sense amplifier whose threshold voltage varies over a wide range, a signal voltage in the bit line must be set lower in order to ensure the same operation margin with respect to variations in power supply voltage or the use environment such as the temperature as in a sense amplifier which performs the initial operation of voltage amplification by an nMOS sense amplifier. For example, the lowest power supply voltage is set higher, or the capacitance of the cell capacitor is set larger. A high power supply voltage however contradicts the object of decreasing the operation voltage. To increase the capacitance of the cell capacitor, the semiconductor manufacturing process must be improved.